The present invention generally relates to controlling the erase operation of nonvolatile memory devices, and, in particular, to control circuits for causing flexible erasing of various parts of the memory devices.
Nonvolatile memory devices, which include nonvolatile memory arrays, have various applications for storing digital information. One such application is for storage of large amounts of digital information for use by digital cameras, as replacements for hard disk within personal computer (PCs) and so forth. Nonvolatile memory arrays are comprised of various types of memory cells, such as EEPROMs, flash.and other types of structures known to those of ordinary skill in the art that have the characteristic of maintaining information stored therein while power is disconnected or disrupted.
In applications enumerated hereinabove and others known in the industry, nonvolatile memory is organized into blocks with each block being identified by a virtual physical block address (VPBA). Each block is generally comprised of a number of sectors (or pages). For example, a block typically includes 16 or 32 sectors. Each sector typically includes various fields such as a user data field and an extension field. The user data field is used to store the user information sought to be saved and the extension field includes field used to store other types of information. The extension field includes an error correction code (ECC) field for storing ECC information, an address field for storing address information and a flag field for storing flag information. In prior art systems, the address field stored within the extension field is a virtual logical block address (VLBA) for identifying the virtual logical block address of the block being written, read or erased. The user data fields and extension fields are included within a sector of information.
Nonvolatile memory units include one or more nonvolatile memory devices or arrays for operation under the direction of a controller circuit that is coupled to a host circuit for receiving certain commands therefrom. For example, the host can read from and/or write digital information to the nonvolatile memory unit through the controller circuit. The controller circuit, in turn, issues certain commands to the nonvolatile memory unit for effectuating the host""s commands. The host identifies storage locations (or units), within the nonvolatile memory array (or unit) within which information is to be written to or read from using logical block addresses whereas the controller translates such addresses into physical block addresses for identifying the actual location within the nonvolatile memory unit in which the block to be addressed is located. Due to the characteristics of nonvolatile memory arrays, the controller circuit must erase an area of nonvolatile memory to which it has previously written prior to re-writing (or re-programming) to the same area. In some examples of nonvolatile memory units having floating gates, during programming, the state of a cell of the nonvolatile memory unit is changed from a logical state of xe2x80x981xe2x80x99 to a logical state of xe2x80x980xe2x80x99 because during erasure of a nonvolatile memory cell, the cell is programmed to a logical state of xe2x80x981xe2x80x99. This is commonly used in nonvolatile memory units having NAND type cell structures whereas in other types of cell structures, such as NOR, the opposite logical states may be used for erase and programming.
The controller circuit currently includes a space manager block having a look-up-table (LUT) that is comprised of volatile memory cells, such as random access memory (RAM), for storing information relating to the blocks stored within the nonvolatile memory unit. This table is used for translating logical block addresses to physical block address, as will be discussed with respect to FIG. 1 shortly. This table is also used to search for free blocks within the nonvolatile memory unit and to maintain the status of the blocks for erasure thereof and other types of information. When power is interrupted to a system including the nonvolatile memory unit and the controller, the information maintained within the LUT is lost due to the volatile nature of the LUT. Thus, upon resumption of power to the system, information within the LUT is reconstructed using the information within the nonvolatile unit.
Referring to FIG. 1, an example of a prior art LUT 1 is shown to comprise rows and columns of volatile memory cells. Specifically, the LUT 1 includes two columns, one for storing address information and another for storing flag information. The address information is VPBA and is stored in the VPBA field 3 and the flag information is stored in the flag field 5. A VLBA 7 is used for addressing each of the rows of the LUT 1. In the example of FIG. 1, the number of rows is shown to be Nxe2x88x921, N being an integer value and representing the number of blocks within the nonvolatile memory unit. The LUT 1 typically resides within the controller, circuit and is used by the controller to translate a VLBA value to a VPBA value by looking up a VPBA 3 value based on the VLBA 7 value. The VLBA is used to address a row of the LUT 1 for finding a corresponding VPBA value in the VPBA 3 field of the addressed row. The controller circuit also looks up a corresponding flag 5 value to determine the status of the block on which it is to perform an operation. For example, to find a free or available block within the nonvolatile memory unit, the controller circuit will look up, using a VPBA value, a corresponding flag field indicating that the block, which is being identified by the VPBA, is xe2x80x98unusedxe2x80x99. Details of the operation of the LUT and related information are shown and explained in the U.S. patent application referred to and incorporated by reference hereinabove.
Currently, during operation, the user data field and extension field of a sector of information is erased at the same time, i.e. using a single erase command to erase both fields. That is, in prior art techniques, a single potential (or voltage level) is used to erase both fields and the single potential may be coupled onto one or more signals for effectuating erasure of both fields. For a better understanding, the reader is now referred to a block diagram of a prior art flash memory device 10, shown in FIG. 2 and referred to as the TH58512FT, manufactured by Toshiba, Inc. of Japan.
The device 10 includes a memory cell array 12 for storing information therein identified by rows and columns (not shown in FIG. 2) of the array 12. These rows and columns are identified by the I/O port 14 and the control signals 16, which are input and output signals to and from the device. The remainder of the blocks shown in FIG. 2 serve as control circuitry for controlling reading, writing and erase operations performed on the array 12. The user data field and extension field of each of the sectors of information reside in one row of the array 18.
It is of particular importance to note that the array 12 is constructed within a main well 18. To selectively erase a block, the voltage applied to well 18 is increased to a voltage level, referred to as, Vpp. This voltage level is generated by the high voltage (HV) generator 20 and included within the signals 22. While not shown in FIG. 2, the control gates of the block to be erased are held at a predetermined erase voltage and the control gates of blocks that are not being erased remain floating or are brought to a non-disturbing voltage (a voltage that avoids erasure and programming of the cell). This, in turn, causes the user data field and extension field of a sector to be erased together. In fact, typically, the user data fields and extension fields of all of the sectors of a block are erased together.
The problem with this approach is that due to the erasure of the user data field with the extension field, there is not much flexibility allowed for organizing the information within the array 18. Multiple updates (or modifications) of the extension field may be performed without affecting the contents of the user data field in the row of the memory unit in which the extension field being modified resides. Additionally, the information maintained within the LUT of the controller circuit is fairly extensive and cannot be trimmed to allow for a smaller volatile memory capacity and therefore less expensive controller circuit.
Therefore, there is a need for a system and method of controlling a nonvolatile memory unit using a controller circuit in a way so as to afford flexibility in organizing information stored within the nonvolatile memory unit and to allow for the manufacturing of an inexpensive controller circuit by using smaller-capacity volatile memory therein.
Briefly, an embodiment of the present invention includes nonvolatile system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit causes erasure of a particular sector of information having a particular user data field and a particular extension field wherein particular user field is erased separately from the particular extension field.
These and other features and advantages of the present invention will become well understood upon examining the figures and reading the following detailed description of the invention.